Cost and power of the system are lowered through the use of 1.2-V VIO SPI NOR Flash.
In the ever-evolving world of technology, the quest for energy efficiency and speed is paramount, especially when interfacing modern sub-10nm System-on-Chips (SoCs) with legacy 1.8V SPI NOR flash memories. A solution to this challenge comes in the form of a dual-voltage SPI NOR architecture.
This innovative design, consisting of a 1.8V core supply and a dedicated 1.2V I/O interface, offers several benefits.
Read Power Reduction
By operating the I/O at 1.2V, power consumption is significantly lower compared to traditional 1.8V interfaces. This reduction in power aligns well with low-voltage SoCs, eliminating the need for level shifters, resulting in standby currents dropping to around 12 µA and deep power-down currents to 200 nA [1].
Faster Page Programming
The architecture achieves a 256-byte page program time of approximately 0.15 ms, which is about 40% faster than conventional 1.8V SPI NOR flash devices [1]. This speed-up primarily stems from the more efficient voltage interface and optimization in flash internal operations enabled by the dual-voltage approach.
Improved Data Throughput
The 1.2V interface maintains compatibility with modern low-voltage SoCs, supporting high-speed SPI access without extra voltage translation overhead. This interface, combined with Quad and Octal SPI standards, can push read throughput up to hundreds of MB/s (e.g., 400 MB/s in some xSPI devices), supporting faster firmware loads and real-time analytics [3][5].
The dual-voltage approach helps maintain this high throughput while minimizing power and system complexity.
Sub-10nm SoCs often operate at core voltages around 1.2V or lower. Having a matching I/O voltage domain in the SPI NOR memory interface reduces interface complexity, power leakage, and silicon area on the SoC for voltage level shifting [1]. This also eases system power management and cost while enabling faster flash read and programming cycles, critical for applications in edge AI, automotive, and IoT devices.
It's important to note that utilizing these devices with a 1.2V SoC requires external level shifters or an SoC with such support built in. Two types of products support the 1.2V SPI NOR flash architecture: pure 1.2V SPI NOR flash and products with a 1.8V core voltage and 1.2V VIO interface voltage.
The dual-voltage 1.8V core / 1.2V I/O SPI NOR flash design reduces power consumption at the interface, improves program speed by about 40%, and supports high data throughput compatible with advanced SPI interface standards, making it well-suited for interfacing modern sub-10nm SoCs with legacy 1.8V SPI NOR flash memories [1][3][5].
[1] GigaDevice's GD25NE SPI NOR flash chip [3] High-speed SPI Access [5] Real-time Analytics
Fig. 1 (unspecified diagram) illustrates the benefits of this design, while Fig. 2 shows the CC_IO pin, an additional pinout for a 1.2V power supply to the I/O pins. Fig. 3 depicts the power-saving benefits of the two-voltage VIO solution.
The performance capabilities of pure 1.2V NOR flash may not be sufficient for higher-performance applications that require a two-voltage solution. However, for emerging market segments utilizing SoCs built on fabrication process nodes of 10nm and below, the dual-voltage SPI NOR architecture offers a significant power-saving advantage (Fig. 3).
The innovative dual-voltage SPI NOR architecture, a solution in the field of data-and-cloud-computing technology, offers a significant power reduction by operating the I/O at 1.2V, thereby aligning well with low-voltage SoCs, as shown in Fig. 1. This technology also facilitates faster page programming, achieving a 256-byte page program time of approximately 0.15 ms, which is about 40% faster than conventional 1.8V SPI NOR flash devices.
