Increased Use of 1.2-V 2nd-Generation SPI NOR Flash Cuts Down System Expenses and Power Consumption
Two-Voltage SPI NOR Architecture Simplifies Flash Memory Interfacing for Sub-10nm SoCs
A new two-voltage SPI NOR flash architecture is making waves in the semiconductor industry, simplifying the interface between advanced sub-10nm System-on-Chips (SoCs) and traditional 1.8V SPI NOR flash memory devices. This innovative solution, which supports dual I/O voltages, allows SoCs operating at low core voltages, such as 1.2V, to communicate directly with 1.8V SPI NOR flash memory without the need for additional level shifters or complex voltage translation circuitry.
This architecture reduces the bill of materials (BOM) and simplifies PCB layout, lowering overall system cost and power consumption. According to recent studies, this two-voltage solution can cut power consumption by around 50% during reads compared to conventional 1.8V SPI NOR flash, and improve page programming speed by approximately 40%.
The two-voltage solution works by having the flash device operate its core at 1.8V while communicating with the SoC at a 1.2V I/O voltage (VIO). This setup, illustrated in Figure 1, involves a power-management IC (PMIC) providing the necessary two voltages.
In terms of performance and power, the two-voltage solution offers several advantages. Read power consumption is significantly reduced, leading to a more power-efficient system. Page programming speed is improved, with 256-byte page program times around 0.15 ms, which is faster than traditional 1.8V SPI NOR flash devices. Data throughput remains similar to conventional 1.8V SPI NOR flash during reads, ensuring no penalty to read speed while gaining power efficiency.
It's worth noting that pure 1.2V NOR flash faces the challenge of delivering the full performance of 1.8V devices due to internal flash operations requiring elevated charge voltage greater than the core voltage.
The two-voltage VIO solution can also save a significant amount of power, as demonstrated in Figure 3. Traditional external flash memory devices support 3.3V or 1.8V power supplies and offer high-speed read, fast program, and fast erase performance.
However, supporting higher-voltage I/O structures like 1.8V can increase SoC die size and cost. Therefore, the two-voltage architecture offers a cost-effective solution for SoC manufacturers looking to interface with traditional flash memory devices while maintaining low power consumption and high-speed performance.
It's important to note that utilizing these devices with a 1.2V SoC may require external level shifters or an SoC with such support built in. Figure 2 shows a typical product setup with 1.8V supplied to the VCC pin, 1.2V to the VCC_IO pin, and an additional 1.2V to the CC_IO pin for the I/O pins.
Overall power usage can be further reduced using power-down modes of GigaDevice's GD25NE SPI NOR flash chip, with standby current draw dropping to 12 μA and deep power-down current draw at 200 nA, as shown in Figure 4.
In conclusion, the two-voltage SPI NOR flash architecture allows sub-10nm SoCs to maintain low-power, high-speed flash memory interfacing while reducing BOM, simplifying PCB design, and improving programming speed without compromising data read performance.
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